栅极触发PDSOI CMOS闩锁效应研究

测试了不同静态栅极触发电压(输入电压)下诱发CMOS闩锁效应需要的电源电压和输出电压(即将闩锁时的输出电压),发现静态栅极触发CMOS闩锁效应存在触发电流限制和维持电压限制两种闩锁触发限制模式,并且此栅极触发电压.输出电压曲线是动态栅极触发CMOS闩锁效应敏感区域与非敏感区域的分界线.通过改变输出端负载电容,测试出了不同电源电压下CMOS闩锁效应需要的栅极触发电压临界下降沿,并拟合出了0 pF负载电容时的临界下降沿,最终得出了PDSOI CMOS电路存在的CMOS闩锁效应很难通过电学方法测试出来的结论.

Study on the Gate Triggered PDSOI CMOS Latch Effect

The supply voltage and output voltage (output voltage just before latch) of CMOS latch effect under different static gate trigger voltage (input voltage) are measured. It is found that there exist two modes of latch limiting condition, the trigger current limit mode and holding voltage limit mode. Besides, the static gate trigger voltage-output voltage curve is the dividing line between the sensitive region and insensitive region of dynamic gate trigger CMOS latch effect. The dynamic gate trigger voltage critical fall time for triggering CMOS latch effect under different supply voltage was tested by changing the output capacitor load and fitted the critical fall time under 0 pF output capacitor load. Finally, it reveals that the CMOS latch effect in PDSOI CMOS circuit is difficult to test by normal electrical method.