| 45nm体硅工艺下使用双-栅氧化层厚度降低SRAM的泄漏功耗 |
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| 引用本文： | 杨松,王宏,杨志家. 45nm体硅工艺下使用双-栅氧化层厚度降低SRAM的泄漏功耗[J]. 半导体学报, 2007, 28(5): 745-749 |
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| 作者姓名： | 杨松 王宏 杨志家 |
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| 作者单位： | 1. 中国科学院沈阳自动化研究所,沈阳,110016;中国科学院研究生院,北京,100049
2. 中国科学院沈阳自动化研究所,沈阳,110016 |
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| 摘 要： | 提出了一种在45nm体硅工艺下使用双-栅氧化层厚度来降低整体泄漏功耗的方法.所提方法具有不增加面积和延时、改善静态噪声边界、对SRAM设计流程的改动很小等优点.提出了三种新型的SRAM单元结构,并且使用这些单元设计了一个32kb的SRAM,仿真结果表明,整体泄漏功耗可以降低50%以上.
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| 关 键 词： | 栅极泄漏电流 SRAM 栅氧化层厚度 静态噪声边界 |
| 收稿时间： | 2015-08-18 |
| 修稿时间： | 2007-01-16 |
Reducing Leakage of SRAM Using Dual-Gate-Oxide-Thickness Transistors in 45nm Bulk Technology |
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| Yang Song, Wang Hong, Yang Zhijia. Reducing Leakage of SRAM Using Dual-Gate-Oxide-Thickness Transistors in 45nm Bulk Technology[J]. Journal of Semiconductors, 2007, In Press. Yang S, Wang H, Yang Z J. Reducing Leakage of SRAM Using Dual-Gate-Oxide-Thickness Transistors in 45nm Bulk Technology[J]. Chin. J. Semicond., 2007, 28(5): 745.Export: BibTex EndNote |
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| Authors: | Yang Song Wang Hong Yang Zhijia |
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| Affiliation: | Shenyang Institute of Automation,Chinese Academy of Sciences,Shenyang 110016,China;Graduate University of Chinese Academy of Sciences,Beijing 100049,China;Shenyang Institute of Automation,Chinese Academy of Sciences,Shenyang 110016,China;Shenyang Institute of Automation,Chinese Academy of Sciences,Shenyang 110016,China |
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| Abstract: | This paper presents a method based on dual-gate-oxide-thickness assignment to reduce the total leakage power dissipation of SRAM in 45nm bulk technology.The proposed technique incurs neither area nor delay overhead and can improve the static noise margin.In addition,it results in a slight change in the SRAM design flow.Three novel SRAM cell configurations are proposed.Simulation results demonstrate that this technique can reduce the total leakage power dissipation of 32kb of SRAM with these configurations by more than 50%. |
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| Keywords: | gate leakage current SRAM gate-oxide-thickness SNM |
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