VSF:CMOS组合电路的静态功耗评估模型

为了解决利用晶体管级电路模拟分析CMOS电路静态功耗时模拟时间随电路规模增大迅速增加的问题,在分析晶体管堆叠效应对标准单元泄漏电流影响的基础上,定义了归一化堆叠系数和电路等效堆叠系数的概念,提出了基于电路有效堆叠系数的静态功耗评估模型.该模型可用于CMOS组合电路静态功耗估算和优化.实验结果表明使用该模型进行静态功耗估算时,不需要进行Hspice模拟.针对ISCAS85基准电路的静态功耗优化结果表明,利用该模型能够取得令人满意的静态功耗优化效果,优化速度大大提高.

VSF: A Leakage Power Evaluation Model for CMOS Combinational Circuits

Two parameters, one called the unified stacking factor (USF) and the other called the circuit virtual stacking factor (VSF), are defined based on the relationship between the transistor stacking effect and the leakage current of standard cells.A VSF-based leakage power evaluation model is then developed and used for evaluating and reducing the leakage power of CMOS combinational circuits.Experiments show that the VSF model is not needed for Hspice simulation when evaluating leakage power.For ISCAS85 benchmark circuits, satisfactory leakage power reduction can be achieved, and the optimization speed can be accelerated greatly.