| 2.5Gb/s/ch 0.18μm CMOS数据恢复电路 |
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| 引用本文： | 刘永旺,王志功,李伟. 2.5Gb/s/ch 0.18μm CMOS数据恢复电路[J]. 半导体学报, 2007, 28(5) |
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| 作者姓名： | 刘永旺 王志功 李伟 |
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| 作者单位： | 东南大学射频与光电集成电路研究所,南京,210096 |
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| 摘 要： | 设计了一个应用于SFI-5接口的2.5Gb/s/ch数据恢复电路.应用一个延迟锁相环,将数据的眼图中心调整为与参考时钟的上升沿对准,因而同步了并行恢复数据,并降低了误码率.采用TSMC标准的0.18μm CMOS工艺制作了一个单通道的2.5Gb/s/ch数据恢复电路,其面积为0.46mm2.输入231-1伪随机序列,恢复出2.5Gb/s数据的均方抖动为3.3ps.在误码率为10-12的条件下,电路的灵敏度小于20mV.
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| 关 键 词： | 数据恢复 延迟锁相环 位同步 |
2.5Gb/s/ch 0.18μm CMOS Data Recovery Circuit |
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| Liu Yongwang,Wang Zhigong,Li Wei. 2.5Gb/s/ch 0.18μm CMOS Data Recovery Circuit[J]. Chinese Journal of Semiconductors, 2007, 28(5) |
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| Authors: | Liu Yongwang Wang Zhigong Li Wei |
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| Abstract: | A 2.5Gb/s/ch data recovery(DR)circuit is designed for an SFI-5 interface.To make the parallel data bit-synchronization and reduce the bit error rate(BER),a delay locked loop(DLL)is used to place the center of the data eye exactly at the rising edge of the data-sampling clock.A single channel DR circuit was fabricated in TSMC's standard 0.18μm CMOS process.The chip area is 0.46mm2.With a 231-1 pseudorandom bit sequence(PRBS)input,the RMS jitter of the recovered 2.5Gb/s data is 3.3ps.The sensitivity of the single channel DR is less than 20mV with 10-12 BER. |
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| Keywords: | data recovery delay locked loop bit-synchronization |
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