一种DSP高可靠性快速数据传输方法的研究

为了避免DSP串行数据传输容易出现数据不同步、误码率高的情况,介绍了一种以DSP为核心,通过FPGA/CPLD扩展外设,采取帧同步和CRC校验的数据传输方法。该设计在DSP数据传输硬件设计的基础上,依靠有限状态机帧同步法和按字节计算CRC,将两种方法相结合定义新的通信协议,将数据存放于所约定的数据帧中进行传输。测试结果表明该方法提高了整个DSP系统的效率、稳定性和安全性,适用于众多信息量大、高速数据传输的场合。

Study on high-reliability and high-speed data transmission on DSP

Asynchronous data and high error rate always happen in DSP data transmission. To avoid those solutions, the paper designs a data transmission method based on DSP, through FPGA/CPLD expansion peripherals, and taken frame synchronization and CRC. Based on a DSP hardware design, a new communication protocol is defined which depends on finite state frame synchronization and calculated by byte CRC. The data stores in the data frame to transport. Through some tests, the method can improve the efficiency, stability, security of the DSP system. It also adapts the occasions which large amount and high-speed data transfer.