| 应用于USB2.0的CMOS锁相环设计 |
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| 引用本文： | 潘瑞雪,周健军,李章全. 应用于USB2.0的CMOS锁相环设计[J]. 信息技术, 2008, 32(7) |
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| 作者姓名： | 潘瑞雪 周健军 李章全 |
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| 作者单位： | 上海交通大学微电子学院,上海,200240 |
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| 摘 要： | 以应用于USB2.0接收端的480MHz锁相环作为设计实例,阐述了锁相环集成电路设计的要素,给出了模块设计思路和仿真波形,并比较了集成电路和印制板电路锁相环的设计方法,展示两种设计思路上的共性和差异.
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| 关 键 词： | 锁相环 集成电路 CMOS 印制板电路 |
Design of CMOS phase-locked loop and its application for USB2.0 |
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| PAN Rui-xue,ZHOU Jian-jun,LI Zhang-quan. Design of CMOS phase-locked loop and its application for USB2.0[J]. Information Technology, 2008, 32(7) |
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| Authors: | PAN Rui-xue ZHOU Jian-jun LI Zhang-quan |
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| Affiliation: | PAN Rui-xue,ZHOU Jian-jun,LI Zhang-quan (School of Microelectronics,Shanghai Jiaotong University,Shanghai 200240,China) |
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| Abstract: | this paper expatiates the factors and means of designing PLL,by a example PLL design which applies in high speed USB 2.0.The PLL working frequency is 480MHz.Compared with the two different design ways of integrated circuit and printed circuit board,the simulation results show the commonness and difference of thought of two designs. |
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| Keywords: | phase-locked loop integrated circuit CMOS printed circuit board |
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