A low-jitter 1.9-V CMOS PLL for UltraSPARC microprocessorapplications |
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Authors: | Hee-Tae Ahn Allstot DJ |
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Affiliation: | Sun Microsyst. Inc., Palo Alto, CA; |
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Abstract: | A phase-locked loop (PLL) for CMOS UltraSPARC microprocessor applications uses a loop filter referenced to a quiet power supply and achieves measured clock period jitter of ±25 ps at 360 MHz. The fully integrated CMOS PLL uses a charge-pump phase/frequency detector, a single-capacitor loop filter, and a feedforward error correction architecture. Loop characteristics are analyzed and verified by measurements. The measured sensitivity of clock period jitter to supply voltage is 2.6 ps/100 mv over an analog supply-voltage range of 1.6-2.1 V; the measured output operating frequency range is 8.5-660 MHz. Fabricated in an area of 310×280 μm2 in a 0.25-μm CMOS process, the PLL dissipates 25 mW from a 1.9-V supply |
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