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Simulating spin systems on IANUS, an FPGA-based computer |
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| Authors: | F Belletti M Cotallo A Cruz LA Fernández A Gordillo A Maiorano F Mantovani E Marinari A Muñoz-Sudupe D Navarro S Pérez-Gaviro JJ Ruiz-Lorenzo SF Schifano D Sciretti A Tarancón R Tripiccione JL Velasco |
| Affiliation: | a Dipartimento di Fisica, Università di Ferrara, I-44100 Ferrara, Italy b INFN, Sezione di Ferrara, I-44100 Ferrara, Italy c Departamento de Física Teórica, Facultad de Ciencias, Universidad de Zaragoza, 50009 Zaragoza, Spain d Instituto de Biocomputación y Física de Sistemas Complejos (BIFI), 50009 Zaragoza, Spain e Departamento de Física Teórica, Facultad de Ciencias Físicas, Universidad Complutense, 28040 Madrid, Spain f Departamento de Física, Facultad de Ciencia, Universidad de Extremadura, 06071 Badajoz, Spain g Dipartimento di Fisica, Università di Roma “La Sapienza”, I-00100 Roma, Italy h Departamento de Ingenieria Electrónica y Comunicaciones, Universidad de Zaragoza, CPS, Maria de Luna 1, 50018 Zaragoza, Spain i Instituto de Investigación en Ingenieria de Aragón (I3A), Universidad de Zaragoza, Maria de Luna 3, 50018 Zaragoza, Spain |
| Abstract: | We describe the hardwired implementation of algorithms for Monte Carlo simulations of a large class of spin models. We have implemented these algorithms as VHDL codes and we have mapped them onto a dedicated processor based on a large FPGA device. The measured performance on one such processor is comparable to O(100) carefully programmed high-end PCs: it turns out to be even better for some selected spin models. We describe here codes that we are currently executing on the IANUS massively parallel FPGA-based system. |
| Keywords: | 05 10 Ln 05 10 -a 07 05 Tp 07 05 Bx |
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