TSV constraints related to temperature excursion, pressure during molding, materials used and handling loads

The current paper focuses on several mechanical aspects of a waferlevel packaging approach using a direct face-to-face Chip-to-Wafer (C2W) bonding of a MEMS device on an ASIC substrate wafer. Requirements of minimized inherent stress from packaging and good decoupling from forces applied in manufacturing and application are discussed with particular attention to the presence of through-silicon vias (TSV) in the substrate wafer. The paper deals with FEM analysis of temperature excursion, pressure during molding, materials used and handling load influence on mechanical stress within the TSV system and on wafer level, which can be large enough to disintegrate the system.