逻辑函数的双逻辑综合与优化

针对传统布尔逻辑在电路面积优化中存在的不足,提出了一种用传统布尔逻辑和Reed-Muller(RM)逻辑相结合的双逻辑优化算法.通过将原逻辑函数的乘积项转化为不相交乘积项,并利用不相交乘积项的位操作,将逻辑函数的覆盖分成2个部分,使之分别适合布尔逻辑综合和RM逻辑综合;同时提出了适合双逻辑函数的逻辑功能验证方法.双逻辑优化算法用C语言编程实现并用MCNC标准电路进行测试.实验结果表明,与单一的布尔逻辑综合结果相比,在绝大多数情况下文中算法可使电路面积获得进一步优化.

Logic Synthesis and Optimization Based on Dual Logic

With the deficiency of the traditional Boolean logic in the logic functions minimization,an algorithm for the logic functions minimization by using both Boolean logic and Reed-Muller(RM) logic is proposed.By converting the product terms of a function into the disjointed products,and using the bit-wise operation of the disjointed products,the logic function’s cover is divided into two parts which are suitable for RM logic implementation and Boolean logic implementation,respectively.Then the function is minimized with both RM logic and Boolean logic(dual logic) at the same time.Further,a method of the functional verification for dual logic is also proposed by checking whether the covers of two functions are equal or not.The proposed algorithm has been implemented in C and tested on MCNC benchmarks.The experimental results show that for the most test cases the proposed dual logic minimization algorithm produces fewer product terms in contrast to the method which only employs Boolean logic.