| 一种高效率的多天线信号检测方案的设计与实现 |
| |
| 引用本文： | 朱捷,席兵,刘勇. 一种高效率的多天线信号检测方案的设计与实现[J]. 计算机应用与软件, 2020, 37(4): 95-100 |
| |
| 作者姓名： | 朱捷 席兵 刘勇 |
| |
| 作者单位： | 重庆邮电大学通信与信息工程学院 重庆 400065;重庆邮电大学通信网与测试技术重点实验室 重庆400065;重庆邮电大学通信网与测试技术重点实验室 重庆400065 |
| |
| 基金项目： | 重庆高校创新团队项目;国家科技重大专项 |
| |
| 摘 要： | 为了满足现代无线通信系统对于信号检测环节高吞吐、低资源消耗的设计需求,针对现有方案从组合逻辑、数据处理能力、模块耦合度等方面进行优化并提出一种高效率的多天线信号检测方案。该方案结构精简、易于流水线实现,结合DDR3高速读写数据的优势并采取基于AXI4-Stream接口封装的技术,极大地提高了检测环节的数据处理效率。以ZYNQ-7100为硬件平台,通过仿真验证了该方案的准确性及优越性。该方案为现有LTE-A系统基带核心处理部分提供了解决方案,同时对其他信号检测类产品IP的设计也有一定参考意义。
|
| 关 键 词： | 信号检测 流水线设计 DDR3 FPGA |
DESIGN AND IMPLEMENTATION OF A HIGH EFFICIENT MULTI-ANTENNA SIGNAL DETECTION SCHEME |
| |
| Zhu Jie,Xi Bing,Liu Yong. DESIGN AND IMPLEMENTATION OF A HIGH EFFICIENT MULTI-ANTENNA SIGNAL DETECTION SCHEME[J]. Computer Applications and Software, 2020, 37(4): 95-100 |
| |
| Authors: | Zhu Jie Xi Bing Liu Yong |
| |
| Affiliation: | (School of Communication and Information Engineering,Chongqing University of Posts and Telecommunications,Chongqing 400065,China;Key Lab on Communication Networks and Testing Technology,Chongqing University of Posts and Telecommunications,Chongqing 400065,China) |
| |
| Abstract: | In order to meet the design requirements of high throughput and low resource consumption for signal detection in modern wireless communication systems,a high efficient multi-antenna signal detection scheme is proposed based on the optimization of existing schemes in combination logic,data processing capability and module coupling.This scheme has the advantages of simplified structure,easy pipeline implementation,DDR3 high-speed data reading and writing,and AXI4-Stream interface encapsulation technology,which greatly improves the data processing efficiency of the detection module.Using ZYNQ-7100 as the hardware platform,the accuracy and superiority of the scheme are verified by simulation.This scheme provides a solution for the baseband core processing part of LTE-A system,and has a certain reference significance for the design of other signal detection products IP. |
| |
| Keywords: | Signal detection Pipeline design DDR3 FPGA0 |
| 本文献已被 维普 万方数据 等数据库收录！ |
|
