基于FPGA的可配置浮点向量乘法单元设计实现

针对目前采用IEEE 754浮点标准设计的FPGA浮点运算器中吞吐率与资源利用率低等问题，提出一种运算精度与运算器数量可配置的并行浮点向量乘法运算单元。通过浮点运算器的指数、尾数位数可配置化设计，提高系统资源利用率，并将流水线技术与并行结构结合，提高数据吞吐率。以EP4CE115型FPGA为测试平台，当配置10组FP14运算器时，系统的逻辑资源占用约为4.2%，峰值吞吐率可达4.5 GFLOPS。结果表明，提出的浮点向量乘法单元有效提高了FPGA资源利用率与运算吞吐率，同时具有高度的可移植性与通用性，适用于FPGA向量乘法运算的加速。

Design and implementation of configurable floating-point vector multiplication unit based on FPGA

Concerning the problems of low throughput and resource utilization of the floating-point arithmetic unit of FPGA designed by IEEE 754 standard, this paper proposed a parallel floating-point vector multiplication unit with configurable operation precision and number of arithmetic units. Through the floating-point arithmetic unit''s exponential and mantissa bits configurable design, it improved system resource utilization, and combined pipeline technology with parallel structure to improve data throughput. Using EP4CE115 FPGA as a test platform, when configured 10 sets of FP14 parallel arithmetic units, the logical resource consumption was about 4.2%, and the peak throughput rate reached 4.5 GFLOPS. The results show that the proposed floating-point vector multiplication unit can effectively improve the resource utilization and operation throughput of FPGA, and has high portability and versatility. It is suitable for the acceleration of the vector multiplication of FPGA.