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A 500-megabyte/s data-rate 4.5 M DRAM |
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| Authors: | Kushiyama N. Ohshima S. Stark D. Noji H. Sakurai K. Takase S. Furuyama T. Barth R.M. Chan A. Dillon J. Gasbarro J.A. Griffin M.M. Horowitz M. Lee T.H. Lee V. |
| Affiliation: | Toshiba Corp., Kawasaki; |
| Abstract: | A 512-kb×9 DRAM with a 500-Mbyte/s data transfer rate was developed. This high data rate was achieved by designing a DRAM core with a very high internal column bandwidth, and coupling this core with a block-oriented, small-swing, synchronous interface that uses skew-canceling clocks. The DRAM has a 1-kbyte×2-line sense-amp cache and is assembled in a 32-pin vertical surface-mount-type plastic package. The measurement results clearly verified the 500-Mbyte/s data rate |
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