Trade-offs in scan path and BIST implementations for RAMs |
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| Authors: | M Nicolaidis O Kebichi V Castro Alves |
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| Affiliation: | (1) Reliable Integrated Systems group, TIMA/INPG, 46 avenue Félix Viallet, 38031 Grenoble Cédex, France |
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| Abstract: | In this article we propose efficient scan path and BIST schemes for RAMs. Tools for automatic generation of these schemes have been implemented. They reduce the design effort and thus allow the designer to select the more appropriate scheme with respect to various constraints. |
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| Keywords: | Aliasing BIST coupling faults RAM test algorithms scan path signature analysis |
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