一种高速LDPC编译码器的设计与实现

分析了基于欧氏几何的LDPC码校验矩阵、生成矩阵的设计方法,讨论了硬件可实现的并行编码器、解码器应具有的结构特点。采用此方法设计了一个长度8176bit、码率3/4的LDPC码。该码字的编码矩阵、解码矩阵都为准循环矩阵,因此非常易于FPGA或ASIC实现,对RAM容量和逻辑单元数量的需求很小,理论吞吐率可达250Mb/s。建立了一个基于FPGA的码字性能测试平台,实测结果表明,该码字的误码平底至少在BER=10-9以下,其性能距离香农限不大于1.4dB。

Design and Implementation of a High-speed LDPC Encoder and Decoder

This paper analyzes the method of designing LDPC codes based on Euclid geometry,and describes the structure of the parallel encoder and decoder that can be implemented in hardware.With this method,an 8176-bit,3/4 rate LDPC code is designed.The generator and parity-check matrix of this code are all quasi-cyclic matrix easy for implementation by FPGA and ASIC,with low requirement on RAMs and logical unit.Its theoretic throughput can be up to 250 Mb/s.With a FPGA-based test-bench established,tt＇s shown that the error-floor of this code is lower than BER=10-9,and the error performance is within 1.4 dB from Shannon limit.