A 900-Mb/s CMOS data recovery DLL using half-frequency clock |
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Authors: | Maillard X Devisch F Kuijk M |
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Affiliation: | ETRO, Vrije Univ., Brussels; |
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Abstract: | A data recovery delay-locked loop (DILL) for nonreturn-to-zero (NRZ) data transmission is described. A reference clock is delayed for triggering a latch that samples the incoming NRZ data stream. The data rate can be twice the reference clock frequency. The circuit has a proportional nondead-zone sampling phase detector that also serves the role of charge pump. A self-correcting function reduces the problem of the finite phase capture range associated with conventional DLLs. The prototype circuit is fabricated in 2.5-V 0.25-μm CMOS and occupies an area of only 270 × 50 μm2. It is demonstrated that at 900-Mb/s NRZ data, jitter is reduced from 118.2- to 31.3-ps rms jitter for a power consumption of only 3 mW |
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