Denotational semantics of a synchronous VHDL subset |
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| Authors: | Dominique Borrione Ashraf Salem |
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| Affiliation: | (1) Laboratoire ARTEMIS, Institut IMAG, BP 53, 38041 Grenoble Cedex 9, France;(2) Computer & Systems Dept., Faculty of Engineering, Ain Shams University, Cairo, Egypt |
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| Abstract: | A denotational definition for a single clock synchronous subset of VHDL is proposed. The different domains for variables and signals, the elaboration of static environments, and the formulation of a simulation algorithm for the sub-language characterize this definition, and distinguish it from more traditional denotational semantics of programming languages. |
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| Keywords: | VHDL elaboration VHDL simulation cycle denotational semantics |
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