一种时序型总线硬件木马的植入与检测

RS总线集成电路在航空航天及工业控制领域具有广泛的应用，随着集成电路硬件木马的检测成为研究热点，作为总线硬件木马研究领域的分支，其设计越来越受关注。在常规时序型硬件木马的基础上，针对RS232总线集成电路，设计一种基于可逆计数器的时序型总线硬件木马。采用Xillix公司的ISE软件在RTL层设计相应的RS232总线Verilog代码，并在常规和可逆时序型硬件木马触发阈值呈等差递增的条件下进行Modelsim仿真分析，结果表明，在总线功能需求复杂和传输数据较多的情况下，可逆时序型木马比常规时序型硬件木马具有灵活性和较低的触发率，隐蔽性更强。

Implantation and Detection of a Sequential Bus Hardware Trojan

RS bus integrated circuit has been widely used in aerospace and industrial control.With the hardware Trojan detection for integrated circuits becoming a research hotspot,as a branch of bus hardware Trojan research field,its design has been paid more and more attention.Based on conventional sequential hardware Trojans,this paper proposes a sequential bus hardware Trojan based on reversible counter for RS232 bus integrated circuits.The corresponding RS232 bus Verilog code is designed in the Register Transfer Level(RTL)layer by using ISE software of Xillix Company.Modelsim-based simulation and analysis are carried out in the case of trigger threshold of conventional and reversible hardware Trojans increasing by equal differences.The simulation results show that in the case of complex bus function requirements and large-scale data transmission,the reversible sequential Trojan has a lower trigger rate and flexibility and higher concealment than the conventional sequential hardware Trojan.