Narrow distribution of threshold Voltage in 4-Mbit MONOS memory-cell array with F-N channel write and direct/F-N tunneling erase operation as a single transistor structure

This paper describes the narrow and nonspreading distribution of threshold voltage in metal-oxide-nitride-oxide semiconductor (MONOS) memory cell array with Fowler-Nordheim (F-N) channel write operation and direct/F-N tunneling erase operation as a single transistor structure. We fabricated a 4-Mbit MONOS memory test chip using 0.25-/spl mu/m technology. The gate length of the memory cell was shrunk to 0.18 /spl mu/m. The distribution of threshold voltage for many operations were evaluated. The range of threshold voltage distribution is small, within 0.5 V in 12-14 V for programming and -8.5 to -9 V for erasing. It was also narrow for program/erase cycles up to 10/sup 4/ and after exposure to temperatures of 300/spl deg/C for 17 h and 150/spl deg/C for 304 h. These characteristics of narrow Vth distribution represent advantages of the MONOS memory device both for nonverify operation in program/erase mode and for low supply voltage operation in read mode. Another advantage is that no anomalous leak cell or tail bit is evident in the data retention result, demonstrating high reliability. The MONOS memory device is a promising candidate for use in cheaper and more scalable gate length fabrication processes compared with floating gate for highly reliable embedded applications.