A CMOS Tunable Transimpedance Amplifier |
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| Authors: | Hwang H-Y Chien J-C Chen T-Y Lu L-H |
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| Affiliation: | Dept. of Electr. Eng. & Graduate Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei; |
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| Abstract: | A tunable transimpedance amplifier (TIA) is presented in this letter. By incorporating a mechanism for gain and bandwidth tuning, the TIA can be adjusted to achieve optimum circuit performance with a lowest bit-error-rate (BER) for high-speed applications. The proposed circuit is implemented in a 0.18-mum CMOS process. Consuming a dc power of 34mW from a 2.0-V supply voltage, the fabricated TIA exhibits a variable -3-dB bandwidth from 3.9 to 7.6GHz while maintaining a transimpedance gain of 52dBOmega. With a 7.5-Gb/s 231-1 pseudo-random bit sequence, the measured input sensitivity of the TIA is -19 dBm at a BER of 10-12 |
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