SSMCB: Low-Power Variation-Tolerant Source-Synchronous Multicycle Bus

In this paper, a variation-tolerant low-power source-synchronous multicycle bus (SSMCB) interconnect scheme is proposed. This scheme is scalable and suitable for transferring data across different clock domains such as those in “many-core” SoCs and in 3-D ICs. SSMCB replaces intermediate flip-flops by a source-synchronous synchronization scheme. Removing the intermediate flip-flops in the SSMCB scheme enables better averaging of delay variations across the whole interconnect, which reduces bit-rate degradation due to within-die process variations. Monte Carlo circuit simulations show that SSMCB eliminates 90% of the variation-induced performance degradation in a six-cycle 9-mm-long 16-bit conventional bus.