The M-machine multicomputer |
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Authors: | Marco Fillo Stephen W Keckler William J Dally Nicholas P Carter Andrew Chang Yevgeny Gurevich Whay S Lee |
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Affiliation: | (1) Artificial Intelligence Laboratory, Laboratory for Computer Science, Massachusetts Institute of Technology, 545 Technology Square, 02139 Cambridge, Massachusetts |
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Abstract: | The M-Machine is an experimental multicomputer being developed to test architectural concepts motivated by the constraints
of modern semiconductor technology and the demands of programming systems. The M-Machine computing nodes are connected with
a 3-D mesh network; each node is a multithreaded processor incorporating 9 function units, on-chip cache, and local memory.
The multiple function units are used to exploit both instruction-level and thread-level parallelism. A user accessible message
passing system yields fast communication and synchronization between nodes. Rapid access to remote memory is provided transparently
to the user with a combination of hardware and software mechanisms. This paper presents the architecture of the M-Machine
and describes how its mechanisms attempt to maximize both single thread performance and overall system throughput. The architecture
is complete and the MAP chip, which will serve as the M-Machine processing node, is currently being implemented. |
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Keywords: | Computer architecture parallelism multithreading coherence |
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