Floorplan-aware application-specific network-on-chip topology synthesis using genetic algorithm technique |
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Authors: | G Lai X Lin |
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Affiliation: | 1. School of Information Science and Technology, Sun Yat-sen University, High Education Mega Center, Guangzhou, 510006, China 2. Department of Math and Information Technology, Hanshan Normal University, Chaozhou, 521041, China
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Abstract: | Communication plays a critical role in the design and performance of multi-core systems-on-chip (SoCs). Networks-on-chip (NoCs) have been proposed as a promising solution to complex on-chip communication problems. As regular NoC topologies are infeasible to satisfy the performance demand for application-specific NoC, customized topology synthesis is therefore desirable. However, NoC topology synthesis problem is an NP-hard problem. In this paper, we propose a suboptimal genetic-algorithm based technique to synthesize application-specific NoC topology with system-level floorplan awareness. The method minimizes the power consumption and router resources while satisfying latency and bandwidth performance constraints. We have evaluated the proposed technique by running a number of representative benchmark applications and the results indicate that our method generates approximate optimal topologies effectively and efficiently for all benchmarks under consideration. |
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