基于JTAG的SoC开发接口设计

文章提出一种应用在SoC系统中的开发接口，用于边界扫描测试、调试、程序流跟踪等。在处理器、外设内核和开源（GDB）、商业的调试／仿真器或边界扫描测试设备之间提供支持。通过IEEE1149．1JTAG协议接口提供外部调试／仿真器、边界扫描测试设备与内核之间的连接。为了使设计具有实用价值和通用性，该设计重点实现了硬件调试功能中最基本最重要的部分，力求结构简洁、工作可靠。文中的设计通过仿真验证，证明其设计可靠、方案可行，具有很好的实用价值。

Design of SoC Development Interface Based on JTAG

The article describes the Development Interface which is used in SoC system for Boundary Scan, test, debug, program flow track and so on. It is an interface between the Processor, peripheral cores and any free (GDB) or commercial debugger/emulator or BS testing device. The external debugger or BS tester connects to the core via a JTAG port which is fully IEEE 1149.1 compatible .To be more practical and more universal, the design mainly achieves to the most basic and important part of hardware debug function in order to get the simple structure and reliable design. After verified by simulation, it can prove the design is reliable, feasible and well practicability, while is also a good reference for relative design.