基于FPGA的高速浮点FFT的实现研究

研究了利用FPGA实现浮点FFT的技术,提出了一种循环控制、RAM访问和蝶形运算三大模块以流水线方式协同工作的方案,结合数据缓冲和并行处理技术,讨论了蝶形运算单元的工作机制。浮点乘法器采用并行Booth编码和3级Wallace压缩树的结构,浮点加法器中采用独立的定点加法器和减法器,使运算得以高速进行。RAM读/写时序和运算参数都可利用寄存器设置。本设计已在Cyclone-Ⅱ系列芯片EP2C8Q208中实现,200MHz主频下,采用外部RAM,完成1024点复数FFT只需750μs。

Research of high speed floating point FFT based on FPGA

The paper discusses technology of implementing floating point FFT on FPGA. Scheme is given that loop control, RAM access and butterfly operation work together in the way of assembly line. Combined with data buffer and parallel processing technology, working mechanism of butterfly operation is discussed. Floating point multiplier uses structure of parallel Booth encoding and three steps Wallace compression tree, independent fixed point adder and subtractor are used in designing floating point adder, so that operation can be completed in high speed. RAM R/W timing and operation parameters can be setted by register. Design has been implemented by Cyclone-Ⅱ series chip EP2C8Q208. At 200 MHz, using of external RAM, time of completing 1 024-point complex FFT is only 750 μs.