| 存储体周期时间分析 |
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| 引用本文： | 谢伦国.存储体周期时间分析[J].计算机工程与科学,1996,18(4):60-65. |
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| 作者姓名： | 谢伦国 |
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| 摘 要： | 在大容量高速并行交叉存取主存系统中,存储体的设计是十分重要的。尽可能地减小存储体周期时间,大大有利于降低系统的设计复杂性和系统成本。本文在介绍一般并行存储体结构和设计要求的基础上,着重对影响存储体周期时间诸因素进行了分析,并具体介绍了一些减少存储体周期时间的措施。
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| 关 键 词： | 存储体周期时间 同步系统 流水线 动态 RAM 静态 RAM |
An Analysis of the Bank Cycle Time |
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| Abstract: | The design of banks is very important in a high-capacity,high-speed parallel interleaving memory system.Reducing the bank cycle time to the full helps to greatly reduce design complexity and system cost.This paper,on the basis of introducing general parallel bank structures and design requirements,focuses on the analysis of fac- tors that affect the bank cycle time and presents a few measures to reduce the bank cycle time. |
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| Keywords: | bank cycle time synchronous system pipeline SRAM DRAM |
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