Design of Power and Area Efficient Digital Down-converters for Broadband Communications Systems |
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| Authors: | A. Pérez-Pascual T. Sansaloni V. Torres V. Almenar J. Valls |
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| Affiliation: | (1) Institute for Telecommunications and Multimedia Applications (ITEAM), Polytechnic University of Valencia, 46730 Grao de Gandía, Valencia, Spain |
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| Abstract: | This paper shows that when a digital receiver is designed utilizing two clock scopes, the digital down-converter can be designed to be efficient in terms of area and power consumption. The main design parameter that contributes to make the design efficient is the relationship between the transition band of the designed filter and its sampling frequency. |
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| Keywords: | Digital down-converter FPGA SDR |
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