QC-LDPC译码器的FPGA设计实现与分析

本文提出一种针对准循环低密度奇偶校验(QC-LDPC)码的双修正型最小和积译码算法，设计了一种基于 FPGA 平台低资源占用率、短处理时延的 QC-LDPC 译码器，并分析了该译码器的译码性能、资源占用率、处理时延等性能，该译码器在不增加实现复杂度和难度的情况下， 能有效减少译码迭代过程中的信息损失，提高译码性能。

Design and Analysis of QC-LDPC Decoder Based on FPGA

For the quasi-cycli low-density parity-check (LDPC) code, this paper proposes a double modified Min-Sum LDPC decoding algorithm. According the algorithm, QC-LDPC decoder is designed based on FPGA, which effectively reduces the hardware consumption rate and processing delay. Finally, the decoding performance, resource consumption and processing delay of this decoder are analyzed in this paper. On the condition that the complexity of algorithm and the difficulty of implementation do not increase, the information losses in iterative decoding can be effectively reduced and the decoding performance can be improved.