| Abstract: | This paper is believed to be one of the first attempts to statistically characterize signal delays of basic CMOS digital building blocks. Analytic expressions in terms of the transistor geometries and technological process variations are provided for fast delay computations, to be used for manufacturing yield optimization, delay variability reduction and general VLSI circuit design for quality. the proposed approach is novel in several ways: (1) It is a combination of an accurate, semi-empirical MOS transistor model with the use of an efficient interpolation technique to link the non-physical model parameters to the ‘designable’ and ‘noise’ factors. (2) It uses several newly developed analytical delay formulae where possible and simple iterative solutions where direct analytical solutions do not exist. (3) the resulting hybrid analytical/iterative models are tuned, if necessary, to enhance the overall statistical accuracy. (4) Local delays are combined together for the analysis of complex combinational VLSI circuits. (5) C-code is generated for specific delay paths to further increase efficiency (improvement in analysis times by two to four orders of magnitude with respect to SPICE, with about 5%-10% accuracy). Examples of statistical delay characterization are used to illustrate the high accuracy of the proposed approach in modelling the influence of the ‘noise’ parameters on circuit delay relative to direct SPICE-based Monte Carlo analysis. the important impact of the proposed approach is that statistical evaluation and optimization of delays in much larger VLSI circuits will become possible. |
