| 基于FPGA平台的媒体系统芯片验证框架 |
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| 引用本文： | 周建,刘鹏,陈科明,梅优良. 基于FPGA平台的媒体系统芯片验证框架[J]. 微电子学, 2006, 36(3): 284-287,291 |
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| 作者姓名： | 周建 刘鹏 陈科明 梅优良 |
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| 作者单位： | 浙江大学,信息与电子工程学系,浙江,杭州,310027 |
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| 摘 要： | 针对媒体系统芯片的不同仿真和验证要求,提出了一种基于FPGA平台的媒体系统芯片验证框架。采用层次化的方法设计软件平台,实现了软件平台的可配置性;采用面向多媒体处理的改进总线结构,实现了硬件平台的可配置和可重用性。基于提出的媒体系统芯片验证框架,快速构建了音频解码系统芯片验证平台,实现了对128 kbps,44.1 kHz立体声AAC LC的实时解码,达到了验证要求。
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| 关 键 词： | 媒体系统芯片 可编程逻辑门阵列 验证框架 层次化 总线结构 |
| 文章编号： | 1004-3365（2006）03-0284-04 |
| 收稿时间： | 2005-09-29 |
| 修稿时间： | 2005-09-292005-12-07 |
Media SOC Verification Framework Based on FPGA Platform |
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| ZHOU Jian,LIU Peng,CHEN Ke-ming,Mei You-liang. Media SOC Verification Framework Based on FPGA Platform[J]. Microelectronics, 2006, 36(3): 284-287,291 |
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| Authors: | ZHOU Jian LIU Peng CHEN Ke-ming Mei You-liang |
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| Abstract: | To meet different requirements of co-simulation and co-verification,a verification framework based on FPGA platform for media SOC is proposed.A hierarchical design method was adopted to make the software reconfigurable.Using improved bus structure method for multimedia processing,reconfigurable and reusable hardware platform was realized.A verification platform based on the framework for an audio decoder SOC has been established and 128 kbps,44.1 kHz stereo AAC LC can be decoded in real-time. |
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| Keywords: | Media SOC FPGA Verification framework Hierarchical Bus-based structure |
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