Mapping 3-D IIR digital filter onto systolic arrays |
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Authors: | F El-Guibaly A Tawfik |
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Affiliation: | (1) Department of Electrical and Computer Engineering, University of Victoria, P.O. Box 3055, V8W 3P6 Victoria, B.C., Canada |
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Abstract: | We present here an efficient systolic implementation for 3-D IIR digital filters. The systolic implementation is obtained by using an algebraic mapping technique. This new mapping technique gives us the choice to mix pipelined variables and broadcast variables. We also determine, through the mapping method, the buffer sizes, the direction of variables propagations and the data feeding and extracting points. The resultant systolic array implementation is a modular structure composed of 2-D filter modules connected by simple buffers. This new systolic implementation is regular, modular and amenable to VLSI Implementation. |
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Keywords: | Multidimensional digital filter algorithm mapping combinatorial geometry systolic array design digital filter design task scheduling processor assignment |
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