A structure-oriented model for determining the substrate spreading resistance in bulk CMOS latch-up paths and its application in holding current prediction

A structure-oriented model has been developed to simulate the actual distribution of majority-carrier current flow paths in the substrate when the parasitic p-n-p-n structure with long-stripe geometry in a CMOS (complementary metal—oxide-semiconductor) circuit is at the latch-up state. Based on this structure-oriented model, the voltage drop across the latch-up path in the substrate can be calculated directly from the structure data. Therefore, the equivalent emitter-base shunting resistance in the substrate can be easily obtained and used to accurately predict the holding current. The two-dimensional numerical simulations have been carried out, based on this structure-oriented model, to obtain the emitter-base shunting resistance associated with the parasitic lateral bipolar transistor in the substrate. The computed substrate shunting resistance and the well emitter-base shunting resistance have been used to calculate the holding current with the help of the measured peak parasitic transistor gains. The predicted holding currents have been found to be in good agreement with the experimental data measured from several p-n-p-n structures, including normal and reversed layouts which are all designed by using the long-stripe geometries. Furthermore, the numerical simulations have been extended to predict the effects of the layout changes of the p-n-p-n structures on the latch-up susceptibility.