Increasing the current-handling capability of TIL GTO thyristors up to its limits—II. Experimental

The theoretical analysis and the developed design criteria for TIL GTO thyristors presented in the first part of this study (Paper I) are validated experimentally. The TO-220-packaged, high-voltage (V_DRM = V_RRM = 1000–1500 V) test TIL GTOs had a total cathode area of 8 mm², of which the area of deep-diffused cathode zones amounted to 3.5 mm². The implementation of optimized technological/geometrical ratios for TIL gate-cathode configuration yielded TIL GTO thyristors with a maximum controllable anode current of 55 A, which is the highest value of I_ATO reported thus far in the open literature for this class of GTOs (identical device area and case). All technological factors and physical effects underlying this achievement are analyzed in detail in this work. The current balancing between the two types of elementary p-n-p-n sections (standard and quasi-nonregenerative) constituting the vertical structure of the novel device is checked experimentally and the impact of this peculiar effect on current-handling capability of TIL GTOs is assessed both qualitatively and quantitatively. The boost of I_ATO up to its limits, ultimately dictated by the thermal impedance junction-to-case Z_thj?c TO-220-packages, was accompanied by a significant increase of the peak turn-off gain (10–20) of these devices at higher levels of anode current and by failure-safe operation of TIL GTOs at high commutation frequencies (up to hundreds of kHz) under heavy load conditions. The developed devices possess an excellent turn-on sensitivity and a high immunity to noise (high dV/dt capability). All the results of this work show clearly that sought-for benefits could be obtained by using the optimized double-interdigitated (TIL) gate-cathode pattern in GTO thyristors. The notation used is the same as in Paper I.