Heterogate junctionless tunnel field-effect transistor: future of low-power devices |
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Authors: | Shiromani Balmukund Rahi Pranav Asthana Shoubhik Gupta |
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Affiliation: | 1.Department of Electrical Engineering,Indian Institute of Technology Kanpur,Kanpur,India;2.Electronics and Nano-scale Engineering Division,University of Glasgow,Glasgow,UK |
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Abstract: | Gate dielectric materials play a key role in device development and study for various applications. We illustrate herein the impact of hetero (high-k/low-k) gate dielectric materials on the ON-current (\(I_{\mathrm{ON}}\)) and OFF-current (\(I_{\mathrm{OFF}}\)) of the heterogate junctionless tunnel field-effect transistor (FET). The heterogate concept enables a wide range of gate materials for device study. This concept is derived from the well-known continuity of the displacement vector at the interface between low- and high-k gate dielectric materials. Application of high-k gate dielectric material improves the internal electric field in the device, resulting in lower tunneling width with high \(I_{\mathrm{ON}}\) and low \(I_{\mathrm{OFF}}\) current. The impact of work function variations and doping on device performance is also comprehensively investigated. |
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