| 基于流水线CORDIC算法的数字下变频实现 |
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| 引用本文： | 郑瑾,葛临东.基于流水线CORDIC算法的数字下变频实现[J].现代雷达,2006,28(10):62-64. |
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| 作者姓名： | 郑瑾 葛临东 |
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| 作者单位： | 解放军信息工程大学,郑州,450002 |
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| 摘 要： | 数字下变频的FPGA实现通常都是基于查表的方法，为了达到高精度要求，常常需要耗费大量的ROM资源去建立庞大的查找表。文中提出了一种基于流水线CORDIC算法的数字下变频实现方案，可有效地节省FPGA的硬件资源，提高运算速度。文章最后给出了该方案的精度分析和实验的仿真结果。
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| 关 键 词： | 数字下变频 CORDIC算法 流水线 FPGA芯片 |
| 收稿时间： | 2006-05-20 |
| 修稿时间： | 2006-08-26 |
Implementation of DDC Based on Pipelined CORDIC Algorithm |
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| ZHENG Jin,GE Lin-dong.Implementation of DDC Based on Pipelined CORDIC Algorithm[J].Modern Radar,2006,28(10):62-64. |
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| Authors: | ZHENG Jin GE Lin-dong |
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| Affiliation: | 1. Beijing Mailbox 947, Unit 7, Beijing 100083, China;2. Information Engineering University, PLA, Zhengzhou 450002, China |
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| Abstract: | The common approach to implement DDC (Digital Down Conversion) on FPGA is based on a look-up table, which requires a huge volume of ROM to achieve high resolution. This paper porposes a pipelined architecture for implementation of DDC on FPGA, which, based on CORDIC algorithm, can save considerable hardware resources and improve the speed performance as well. Finally, a quantization error analysis and simulation results are presented. |
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| Keywords: | DDC(Digital Down Conversion) CORDIC algorithm pipeline FPGA chip |
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