8位高速RISC微处理器的设计

本文按照自上而下的系统级设计思想,进行系统功能结构的划分。利用VerilogHDL进行寄存器传输级的描述,完成了与其他同类产品兼容的,具有取指、译码、执行和回写四级流水线,一条指令只用一个时钟周期(个别跳转指令例外)的RISC微处理器IP软核的设计。并通过版图设计的考虑,探讨了提高所设计微处理器的时钟速度的方法。

Design of High-speed 8-bits RISC Microprocessor

In this paper, according to the system level design philosophy of top to down, the IP core which is compatible with other similar products has been completed by the analyzing the architecture and instruction set of RISC structure and using the Verilog HDL for describing RTL. There are four pipelines, such as instruction fetch, instruction decode, executive and write back in the core, and each instruction can cost only one cycle of the clock . Moreover, layout design is also included in this paper and some methods which can be used to improve the clock speed of the micro-processor are discussed, too.