用于高能物理实验电子读出芯片的低噪声锁相环芯片设计

基于TSMC 180 nm工艺设计并流片测试了一款用于高能物理实验的电子读出系统的低噪声、低功耗锁相环芯片。该芯片主要由鉴频鉴相器、电荷泵、环路滤波器、压控振荡器和分频器等子模块组成，在锁相环电荷泵模块中，使用共源共栅电流镜结构精准镜像电流以减小电流失配和用运放钳位电压进一步减小相位噪声。测试结果表明，该锁相环芯片在1.8 V电源电压、输入50 MHz参考时钟条件下，可稳定输出200 MHz的差分时钟信号，时钟均方根抖动为2.26 ps(0.45 mUI),相位噪声在1 MHz频偏处为-105.83 dBc/Hz。芯片整体功耗实测为23.4 mW,锁相环核心功耗为2.02 mW。

Design of Low Noise PLL for Electronic Readout Chip in High Energy Physics Experiment

A low noise and low power phase locked loop (PLL) chip for the electronic readout system of high energy physics experiments was designed and tested based on the TSMC process of 180nm. The chip was mainly composed of frequency and phase discriminator, charge pump, loop filter, voltage controlled oscillator, frequency divider and other sub-modules. In the phase-locked loop charge pump module, the cascade current mirror was used to accurately mirror the current to reduce the electrical loss and the operation amplifier clamp voltage was used to further reduce the phase noise. The test results show that the PLL chip can stably output 200MHz differential clock signal under the condition of 1.8V power supply voltage and 50MHz reference clock input. The RMS clock jitter is 2.26ps (0.45mUI), and the phase noise is -105.83dBc/Hz at the frequency offset of 1MHz. The measured power consumption of the overall chip is 23.4mW and the core power consumption of the PLL is 2.02mW.