FIR滤波器的FPGA实现及其仿真研究

本文提出了一种采用现场可编程门阵列器件FPGA实现FIR字滤波器硬件电路的方案,该方案基于只读存储器ROM查找表的分布式算法。并以一个十六阶低通FIR数字滤波电路在ALTERA公司的CYCLONE系列FPGA芯片上的实现为例说明了设计过程。所设计电路通过软件验证和硬件仿真,结果表明电路工作正确可靠,满足设计要求,性能优于用DSP和传统方法实现的FIR滤波器。

FIR filter''''s simulation and realization on FPGA

This paper discusses a method to design the FIR filter on FPGA, on the basis of distributed arithmetic, by using ROM based LUT. It introduces the designing process in detail by presenting an instance of realizing a 16 tap FIR filter on Altera's Cyclone FPGA. Simulating experiments, both on software and hardware, also have proved the efficiency of the method compared with common algorithm and DSP filter.