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Bit synchronisation in Gbit/s range using dual gate GaAs m.e.s.f.e.t.s |
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| Authors: | Beneking H. Filensky W. Ponse F. |
| Affiliation: | Aachen Technical University, Institute of Semiconductor Electronics, Aachen, West Germany; |
| Abstract: | Bit synchronisation at 1 and 2 Gbit/s including pulse width reduction is achieved using dual gate GaAs m.e.s.f.e.t.s. Circuits and time behaviour of input-, clock- and output signals are shown. |
| Keywords: | |