| 宽带低相位噪声锁相环型频率合成器的CMOS实现 |
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| 引用本文： | 陈作添,吴烜,唐守龙,吴建辉. 宽带低相位噪声锁相环型频率合成器的CMOS实现[J]. 半导体学报, 2006, 27(10): 1838-1843 |
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| 作者姓名： | 陈作添 吴烜 唐守龙 吴建辉 |
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| 作者单位： | 东南大学国家专用集成电路系统工程技术研究中心,南京,210096 |
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| 摘 要： | 用0.25μm标准CMOS工艺实现了单次变频数字有线电视调谐器中的频率合成器.它集成了频率合成器中除LC调谐网络和有源滤波器外的其他模块.采用I2C控制三个波段的VCO相互切换,片内自动幅度控制电路和用于提升调谐电压的片外三阶有源滤波器,实现VCO的宽范围稳定输出.改进逻辑结构的双模16/17预分频器提高了电路工作速度.基于环路的行为级模型,对环路参数设计及环路性能评估进行了深入的讨论.流片测试结果表明,该频率合成器的锁定范围为75～830MHz,全波段内在偏离中心频率10kHz处的相位噪声可以达到-90.46dBc/Hz,100kHz处的相位噪声为-115dBc/Hz,参考频率附近杂散小于-90dBc.
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| 关 键 词： | 频率合成器 相位噪声 锁相环 压控振荡器 预分频器 |
| 收稿时间： | 2015-08-18 |
| 修稿时间： | 2006-04-11 |
CMOS Implementation of a Wideband Low Phase Noise PLL Frequency Synthesizer |
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| Chen Zuotian, Wu Xuan, Tang Shoulong, Wu Jianhui. CMOS Implementation of a Wideband Low Phase Noise PLL Frequency Synthesizer[J]. Journal of Semiconductors, 2006, In Press. Chen Z T, Wu X, Tang S L, Wu J H. CMOS Implementation of a Wideband Low Phase Noise PLL Frequency Synthesizer[J]. Chin. J. Semicond., 2006, 27(10): 1838.Export: BibTex EndNote |
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| Authors: | Chen Zuotian Wu Xuan Tang Shoulong Wu Jianhui |
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| Affiliation: | National Engineering Research Center for Application-Specific Integrated Circuit Systems,Southeast University,Nanjing 210096,China;National Engineering Research Center for Application-Specific Integrated Circuit Systems,Southeast University,Nanjing 210096,China;National Engineering Research Center for Application-Specific Integrated Circuit Systems,Southeast University,Nanjing 210096,China;National Engineering Research Center for Application-Specific Integrated Circuit Systems,Southeast University,Nanjing 210096,China |
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| Abstract: | A prototype PLL frequency synthesizer for a single-conversion digital cable TV tuner is integrated in a standard 0.25μm CMOS process, except for the LC tanks and active loop filter.Three-band VCOs with AAC (auto-amplitude control) circuit switches controlled by I2C provide a wideband amplitude stable output.A third order active loop filter is used to boost the tuning voltage.A 16/17 dual-modulus prescaler with on improved logic structure increases the speed.With the help of the system-behavior model of the loop,the design of the loop parameters and the evaluation of the frequency synthesizer are discussed in depth.The measurements results show that the locked range of the frequency synthesizer is 75 to 830MHz,the phase noise in the locked band can reach -90.46dBc/Hz at a 10kHz offset and -115dBc/Hz at a 100kHz offset.The spurious signal near the reference frequency is less than -90dB. |
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| Keywords: | :frequency synthesizer phase noise phase-locked loop VCO prescaler |
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