Performance investigations of novel dual-material gate (DMG) MOSFET with dielectric pockets (DP)

Dual-material gate MOSFET with dielectric pockets (DMGDP MOSFET) is proposed to eliminate the potential weakness of the DP MOSFET for CMOS scaling toward the 32 nm gate length and beyond. The short-channel effects (SCE) can be effectively suppressed by the insulator near the source/drain regions. And the suppression capability can be even better than the DP MOSFET due to the drain bias absorbed by the screen gate. The speed performance and electronic characteristics of the DMGDP MOSFET are comprehensively studied. Compared to the experimental data from Jurczak et al., the DMGDP PMOSFET exhibits good subthreshold characteristics and the on-state current is almost the twice that of the DP PMOSFET. The intrinsic delay of the NMOS reaches 21% greater than the DP MOSFET for 32 nm node. The higher f _T of 390 GHz is achieved, which is a 32% enhancement in comparison with the DP MOSFET when the gate length is 50 nm. Finally, the design guideline and the optimal regions of the DMGDP MOSFET are discussed. Supported by the National Natural Science Foundation of China (Grant No. 60206006), Program for the New Century Excellent Talents of Ministry of Education of China (Grant No. 681231366), and the National Defense Pre-Research Foundation of China (Grant No. 51308040103)