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Parallel associative combinator evaluation II
Authors:Martin Waite   Bret Giddings  Simon Lavington
Affiliation:

Department of Computer Science, University of Essex, Winenhoe Park, Colchester, Essex, CO4 3SQ, UK

Abstract:A new evaluation model for SK combinator expressions is presented and used as a basis for the design of a novel processor. The resulting machine architecture resembles a dataflow ring, but executions are constrained to be fully lazy. An automatic dynamic load sharing mechanism for a distributed multiprocessor architecture is suggested, and initial simulation results are presented.
Keywords:Novel parallel architecture   fine-grained combinator reduction
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