Fabrication and Circuit Modeling of NMOS Inverter Basedon Quantum Dot Gate Field-Effect Transistors |
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Authors: | Supriya Karmakar John A. Chandy Mukesh Gogna Faquir C. Jain |
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Affiliation: | 1. Department of Electrical and Computer Engineering, University of Connecticut, 371, Fairfield Way, U-2157, Storrs, CT, 06269-2157, USA 2. Intel Corporation, Hillsboro, OR, 97124, USA
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Abstract: | This paper presents the fabrication of a negative-channel metal–oxide–semiconductor (NMOS) inverter based on quantum dot gate field-effect transistors (QDG-FETs). A QDG-FET produces one intermediate state in its transfer characteristic. NMOS inverters based on a QDG-FET produce three states in their transfer characteristic. The generation of the third state in the inverter characteristic makes this a promising circuit element for multivalued logic implementation. A circuit simulation result based on the Berkley simulation (BSIM) circuit model of the QDG-FET is also presented in this paper, predicting the fabricated device characteristic. |
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