| TM1300 DSP芯片JTAG接口仿真器的设计 |
| |
| 引用本文： | 李智明,王超. TM1300 DSP芯片JTAG接口仿真器的设计[J]. 南通纺织职业技术学院学报, 2007, 7(2): 1-6 |
| |
| 作者姓名： | 李智明 王超 |
| |
| 作者单位： | 南通纺织职业技术学院,南通,226007;安徽机电职业技术学院,芜湖,241000 |
| |
| 摘 要： | 目前JTAG广泛应用于FPGA、DSP中,JTAG是芯片调试的重要手段.采用TM1300的测试访问端口控制器TAP中的Test Data In、Test Data Out、Test Clock、Test Mode Select信号管脚,通过CPLD、电平匹配、实现与PC机增强型并口协议并口的硬件连接.在分析JTAG接口的工作过程和时序的基础上,编写出了基于CPLD的JTAG仿真器相应的驱动程序,具体实现了PC的并行口与TM1300的数据通讯.该方法采用基于CPLD的JTAG仿真器,其可靠性、稳定性和经济性在实际系统中得到了充分的验证,对缩短产品的研发和调试周期,具有实际意义.
|
| 关 键 词： | EPP TM1300仿真器 JTAG CPLD |
| 文章编号： | 1671-6191（2007）02-0001-06 |
| 修稿时间： | 2007-04-03 |
A Design of Trimedia 1300 DSP Chip JTAG Interface Simulator |
| |
| LI Zhi-ming,WANG Chao. A Design of Trimedia 1300 DSP Chip JTAG Interface Simulator[J]. Journal of Nantong Textile Vocational Technology college, 2007, 7(2): 1-6 |
| |
| Authors: | LI Zhi-ming WANG Chao |
| |
| Affiliation: | 1. Nantong Textile Vocational Technology College,Nantong 226007,China; 2. Anhui Technical College Of Mechanical and Electrical Engineering,Wuhu 241000,China |
| |
| Abstract: | The JTAG is widely applied in FPGA & DSP currently and it is the prominent means of chip adjustment.This thesis adopts the four pins of TAP:Test Data In,Test Data Out,Test Clock,Test Mode Select of TM1300 and realizes the hardware connection with EPP of PC through CPLD,electric level match.Then on the basis of analysis of working process and time order of JTAG interface,the author compiles the drive program corresponding to JTAG built on CPLD and achieves the goal of the data communication between EPP of PC and Trimedia1300.This design makes use of the simulator JTAG built on CPLD,whose credibility,stability and economy have won full verification in real system.It is significant in shortening the period of research and development and adjustment. |
| |
| Keywords: | EPP JTAG CPLD |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ |
|
