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| 5加数并行加法器及其进位接口 | |
| 引用本文： | 刘杰,易茂祥. 5加数并行加法器及其进位接口[J]. 计算机工程, 2010, 36(1): 251-252 |
| 作者姓名： | 刘杰 易茂祥 |
| 作者单位： | 1. 阜阳师范学院物理与电子科学学院,阜阳,236041 2. 台肥工业大学应用物理系,合肥,230009 |
| 基金项目： | 安徽省高校省级自然科学研究基金 |
| 摘 要： | 传统加法器在处理多操作数累加时，必须进行多次循环相加操作。针对该问题设计5操作数并行加法器及其高速进位接口。电路采用多操作数并行本位相加和底层进位级联传递的方式，在一定程度上实现多操作数间的并行操作，减少相加次数。模拟结果验证了该加法器的设计合理性，证明其能缩短累加时间、提高运算效率。 |
| 关 键 词： | 加法器 超前进位加法器 进位接口 |
| 修稿时间： | |
Parallel Adder with Five Addend and Its Carry Interface |
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| LIU Jie,YI Mao-xiang. Parallel Adder with Five Addend and Its Carry Interface[J]. Computer Engineering, 2010, 36(1): 251-252 | |
| Authors: | LIU Jie YI Mao-xiang |
| Affiliation: | (1. School of Physics and Electronic Science, Fuyang Normal College, Fuyang 236041; 2. Department of Applied Physics, Hefei University of Technology, Hefei 230009) |
| Abstract: | Traditional adder must do several times of cyclic addition operation in processing of multi-operand accumlation. Aiming at this problem, this paper designs a five addend parallel adder and its high speed carry interface. Because the circuit uses parallel own department addition of multi-operands and bottom layer carry cascade connection transmission mode, the parallel operation between multi-operands is realized and addition times are reduced. Simulation results verify the design reasonability of the adder and prove that it can shorten addition time, enhance operation efficiency. |
| Keywords: | adder Carry Look-Ahead Adder(CLAA) carry interface |
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