| 基于SOC的IIC总线IP核设计 |
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| 引用本文： | 杨峰. 基于SOC的IIC总线IP核设计[J]. 数字社区&智能家居, 2010, 0(6) |
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| 作者姓名： | 杨峰 |
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| 作者单位： | 兰州交通大学; |
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| 摘 要： | 该文详述了一种基于wishbone总线接口的IIC总线控制器IP核设计,给出了该IP核的系统接口以及各个子模块的详细设计方法,并对该IP核进行了仿真和验证。
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| 关 键 词： | IIC总线 IP核 WISHBONE总线 片上系统 verilogHDL |
Design of IIC Bus IP Core Based On SOC |
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| YANG Feng. Design of IIC Bus IP Core Based On SOC[J]. Digital Community & Smart Home, 2010, 0(6) |
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| Authors: | YANG Feng |
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| Affiliation: | Lanzhou Jiaotong University;Lanzhou 730070;China |
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| Abstract: | This paper presents design of an IIC bus IP core based on soc with a wishbone inter face.it describes system architecture and de-tail design mehod of every sub-module and gives methods about simulation and verification. |
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| Keywords: | IIC bus IP core Wishbone interface SOC Verilog HDL |
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