A 2-V 900-MHz monolithic CMOS dual-loop frequency synthesizer forGSM receivers |
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| Authors: | Yan W.S.T. Luong H.C. |
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| Affiliation: | Dept. of Electr. & Electron. Eng., Hong Kong Univ.; |
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| Abstract: | A 900-MHz monolithic CMOS dual-loop frequency synthesizer suitable for GSM receivers is presented. Implemented in a 0.50-μm CMOS technology and at a 2-V supply voltage, the dual-loop frequency synthesizer occupies a chip area of 2.64 mm2 and consumes a low power of 34 mW. The measured phase noise of the synthesizer is -121.8 dBc/Hz at 600-kHz offset, and the measured spurious levels are -79.5 and -82.0 dBc at 1.6 and 11.3 MHz offset, respectively |
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