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基于次态共卡诺图的同步时序电路快速分析法
引用本文:雷升印.基于次态共卡诺图的同步时序电路快速分析法[J].武汉理工大学学报,2001,23(5):37-39.
作者姓名:雷升印
作者单位:武汉理工大学
摘    要:针对应用代数法和列表法分析同步时序电路计算逻辑值工作量繁杂且容易出错的缺点,提出了一种基于时序电路的次态共卡诺图的快速分析法,该方法首先求出时序电路中各触发器的次态表达式,然后把各次态表达式表示在同一张卡诺图上,最再把它转换成状态图,以实例介绍了该分析法的应用,展示了其分析速度快,结果又准确的特点。

关 键 词:数字电路  时序逻辑  快速分析法  次态共卡诺图法  同步时序电路
文章编号:1000-2405(2001)05-0037-03
修稿时间:2000年12月4日

A Fast Analyze Method of Synchronized Sequence Circuits with Common Karnaugh Map
Lei Shengyin.A Fast Analyze Method of Synchronized Sequence Circuits with Common Karnaugh Map[J].Journal of Wuhan University of Technology,2001,23(5):37-39.
Authors:Lei Shengyin
Affiliation:Lei Shengyin
Abstract:Due to the disadvatages of using applied algebra and scheme to calculate the synchronized sequence circuits logic val-ue, the article proposes a quick component analysis method ,which is based on sequence circuit on Karnaugh map . This method calculates the next status functions of each trigger in a sequenced circuit and shows all the functions within one Karnaugh map, and then converts into status chart. Applications of this method are demonstrated at the end of the aticle to show its quickness and accuracy.
Keywords:digital circuit  sequential logic  analyze method  
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