基于超窄数据的低功耗数据Cache方案

降低耗电量已经成为当前最重要的设计问题之一.现代微处理器多采用片上Cache来弥合主存储器与中央处理器(CPU)之间的巨大速度差异,但Cache也成为处理器功耗的主要来源,设计低功耗的Cache存储体变得越来越重要.仅需要很少的几位就可以存储的超窄数据(VNV)在Cache的存储和访问中都占有很大的比例.据此,提出了一种基于超窄数据的低功耗Cache结构(VNVC).在VNVC中,数据存储体被分为低位存储体和高位存储体两部分.在标志位控制下,用来存放超窄数据的高存储单元将被关闭,以节省其动态和静态功耗.VNVC仅通过改进存储体来获得低功耗,不需要额外的辅助硬件,并且不影响原有Cache的性能,所以适合于各种Cache组织结构.采用12个Spec2000测试程序的仿真结果表明,4位宽度的超窄数据可以获得最大的节省率,平均可节省动态功耗29.85%、静态功耗29.94%.

A Low Power Data Cache Design Based on Very Narrow-Width Value

Today, lowering power consumption has become one of the most critical design concerns. Most modern microprocessors employ on-chip caches to bridge the enormous speed disparities between the main memory and the central processing unit (CPU), but these caches consume a significant fraction of the total power. It becomes increasingly important to design power-efficient cache memories. The very narrow-width values (VNVs) that need only a few bits to store occupy a large portion of cache access and storage. Based on this observation, a low power very narrow-width value cache (VNVC) which exploits the prevalence of VNVs stored in the cache is proposed. In VNVC, the data array is divided into low-bit array and high-bit array. At the control of an additional flag bit, the higher bits of the data cells that store VNV are closed to save its dynamic and static power consumption. VNVC achieves low power consumption only by the modification of the data array without any extra assistant hardware, and does not impact cache performance. Thus it suits for most kinds of cache organization. Experiments on 12 Spec 2000 benchmarks show that on average 4-bit width VNVC can obtain the best improvement, providing 29.85% dynamic and 29.94% static power reduction.