Ultra thin ICs and MEMS elements: techniques for wafer thinning,stress-free separation,assembly and interconnection |
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Authors: | M Feil C Alder G Klink M König C Landesberger S Scherbaum G Schwinn H Spöhrle |
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Affiliation: | (1) Fraunhofer Institute for Reliability and Microintegration, Munich Division (IZM-M), Hansastrasse 27d, D-80686 Munich, Germany, DE |
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Abstract: | Ultra thin chips with a thickness below 30 μm offer low system height, low topography and show enhanced mechanical flexibility.
These properties enable diverse use possibilities and new applications. However, advanced wafer thinning, adapted assembly
and interconnection methods are required for this technology. A new process scheme is proposed that allows manufacturing of
ultra thin fully processed wafers. Secure handling is achieved by means of carrier substrates using reversible adhesive tapes
for connection of support and device wafers. Well established backgrinding and etching techniques are used for wafer thinning.
To avoid mechanical damage of thin ICs the “Dicing-by-Thinning” (DbyT) concept is introduced to process flow. Best results
are obtained when preparing dry etched chip grooves at front side of device wafer and opening these trenches during backside
thinning. The new process scheme was also applied to wafers with highly topographic surfaces. Results of 40 μm thin wafers
with 15 μm high Nickel bumps are presented. Three different assembly methods are described, interconnection through the thin
chip, face down assembly and isoplanar contacting.
Received: 6 July 2001/Accepted: 26 February 2002
The authors would like to thank M. Küchler (IZM Chemnitz) for preparing and performing trench etching process and A. Ostmann
(IZM Berlin) for performance of nickel bumping process.
This paper was presented at the Conference of Micro System Technologies 2001 in March 2001. |
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